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SH7040 Datasheet, PDF (18/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
Section
Appendix B Block
Diagrams
Figure B.19
PB4/IRQ2/POE2/
CASH,PB3/IRQ1/
POE1/CASL
Block Diagram
(F-ZTAT Version)
Page Description
844 Note added
On-chip flash memory*
A17
Note: * Only when n = 4.
Appendix C Pin
865
States
Table C.1 Pin
Modes During Reset,
Power-Down, and
Bus Right Release
Modes (144 Pin)
Table amended
Pin Function
Class Pin Name
Clock CK
System RES
control MRES
WDTOVF
BREQ
BACK
Interrupt NMI
IRQ0–IRQ7
IRQOUT (PD30)
IRQOUT (PE15)
Address A0–A21
bus
Data bus D0–D31
Bus
WAIT
control RD/WR, RAS
CASH, CASL,
CASLH, CASLL
RD
CS0, CS1
CS2, CS3
WRHH, WRHL,
WRH, WRL
AH
DMAC DACK0, DACK1
(PD26, PD27)
DACK0, DACK1
(PE14, PE15)
DRAK0, DRAK1
DREQ0, DREQ1
Pin modes
Reset
Power-OnManual
O
O
Power-Down Bus Right
Standby Sleep Release
H*1
OO
I
I
I
Z*4
I
Z
O*3
O*3
O
Z*4
I
Z
Z*4
O
Z
I
I
I
I
OO
I
I
OL
I
I
Z*4
I
Z*4
O
Z*4
O
O*2
O
I
I
I
Z
I
I
H*1
HO
Z
HO
Z
OZ
Z*4
I/O
Z
I/O Z
Z*4
I
Z
I
Z
Z*4
O
O
OZ
Z*4
O
O
OZ
H
O
H
O
Z*4
O
H
O
Z*4
O
Z*4
O
Z*4
O
Z*4
O
Z*4
I
Z
OZ
Z
OZ
Z
OZ
Z
OZ
Z
OZ
O*1
OO
Z
OO
O*1
OO
Z
I
I
Standby in Bus
Right Release
O
I
Z
O
I
L
I
Z
H*1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
O*1
Z
O*1
Z