SH7040 Datasheet, PDF (735/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation
in RAM. When RAMS = 1, all flash memory block are program/erase-protected. This bit is
ignored when the on-chip ROM is disabled.
Bit 2: RAMS
0
1
Description
Emulation not selected
Program/erase protect of all flash memory blocks is disabled (Initial value)
Emulation selected
Program/erase protect of all flash memory blocks is enabled
• Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 22.5.)
Table 22.5 Separation of the Flash Memory Area
Addresses
H'FFF800–H'FFFBFF
H'03F000–H'03F3FF
H'03F400–H'03F7FF
H'03F800–H'03FBFF
H'03FC00–H'03FFFF
Block Name
RAM area 1kB
EB8 (1kB)
EB9 (1kB)
EB10(1kB)
EB11(1kB)
RAMS
0
1
1
1
1
RAM1
*
0
0
1
1
RAM0
*
0
1
0
1
697