SH7040 Datasheet, PDF (362/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.4 Operation
12.4.1 Overview
The operation modes are described below.
Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The
TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external
event counter. General registers (TGR) can be used as output compare registers or input capture
registers.
Synchronized Operation: The TCNT of a channel set for synchronized operation does a
synchronized preset. When any TCNT of a channel operating in the synchronized mode is
rewritten, the TCNTs of other channels are simultaneously rewritten as well. The timer
synchronization bits of the TSYR registers of multiple channels set for synchronous operation can
be set to clear the TCNTs simultaneously.
Buffer Operation: When TGR is an output compare register, the buffer register value of the
corresponding channel is transferred to the TGR when a compare-match occurs. When TGR is an
input capture register, the TCNT counter value is transferred to the TGR when an input capture
occur simultaneously the value previously stored in the TGR is transferred to the buffer register.
Cascade Connection Operation: The channel 1 and channel 2 counters (TCNT1 and TCNT2)
can be connected together to operate as a 32-bit counter.
PWM Mode: In PWM mode, a PWM waveform is output. The output level can be set by the
TIOR register. Each TGR can be set for PWM waveform output with a duty cycle between 0%
and 100%.
Phase Counting Mode: In phase counting mode, the phase differential between two clocks input
from the channel 1 and channel 2 external clock input pins is detected and the TCNT counter
operates as an up/down counter. In phase counting mode, the corresponding TCLK pins become
clock inputs and TCNT functions as an up/down counter. It can be used as a two-phase encoder
pulse input.
Reset-Synchronized PWM Mode: Three-phase positive and negative PWM waveforms can be
obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point
on one side). When set for reset-synchronized PWM mode, TGR3A, TGR3B, TGR4A, and
TGR4B automatically become output compare registers. The TIOC3A, TIOC3B, TIOC4A,
TIOC4B, TIOC4C, and TIOC4D pins also become PWM output pins, and TCNT3 and TCNT4
become upcounters. TCNT4, TGR4A, and TGR4B are isolated from TCNT4.
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