SH7040 Datasheet, PDF (396/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Register operation
In complementary PWM mode, nine registers are used, comprising compare registers, buffer
registers, and temporary registers. Figure 12.40 shows an example of complementary PWM
mode operation.
The registers which are constantly compared with the counters to perform PWM output are
TGR3B, TGR4A, and TGR4B. When these registers match the counter, the value set in bits
OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGR3D, TGR4C, and TGR4D.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer
register. The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb
interval.
The value transferred to a temporary register is transferred to the compare register when
TCNTS for which the Tb interval ends matches TGR3A when counting up, or H'0000 when
counting down. The timing for transfer from the temporary register to the compare register can
be selected with bits MD3–MD0 in the timer mode register (TMDR). Figure 12.40 shows an
example in which the mode is selected in which the change is made in the trough.
In the tb interval (tb2 in figure 12.40) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is
compared with the counter. In this interval, therefore, there are two compare registers for one-
phase output, with the compare register containing the pre-change data, and the temporary
register containing the new data. In this interval, the three counters—TCNT3, TCNT4, and
TCNTS—and two registers—compare register and temporary register—are compared, and
PWM output controlled accordingly.
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