SH7040 Datasheet, PDF (284/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

11.3.9 Bus Mode and Channel Priority Order
When a given channel is transferring in burst mode, and a transfer request is issued to channel 0,
which has a higher priority ranking, transfer on channel 0 begins immediately. If the priority level
setting is fixed mode (CH0 > CH1), channel 1 transfer is continued after transfer on channel 0 are
completely ended, whether the channel 0 setting is cycle steal mode or burst mode.
When the priority level setting is for round robin mode, transfer on channel 1 begins after transfer
of one transfer unit on channel 0, whether channel 0 is set to cycle steal mode or burst mode.
Thereafter, bus right alternates in the order: channel 1 > channel 0 > channel 1 > channel 0.
Whether the priority level setting is for fixed mode or round robin mode, since channel 1 is set to
burst mode, the bus right is not given to the CPU. An example of round robin mode is shown in
figure 11.14.
CPU
DMAC
ch1
DMAC
ch1
DMAC
ch0
ch0
DMAC
ch1
ch1
DMAC
ch0
ch0
DMAC
ch1
DMAC
ch1
CPU
CPU
DMAC ch1
burst mode
DMAC ch0 and ch1
round-robin mode
DMAC ch1
burst mode
CPU
Priority: Round-robin mode
ch0: Cycle-steal mode
ch1: Burst mode
Figure 11.14 Bus Handling when Multiple Channels Are Operating
11.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. For details, see section 10, Bus State Controller (BSC).
DREQ Pin Sampling Timing and DRAK Signal: In external request mode, the DREQ pin is
sampled by either falling edge or low-level detection. When a DREQ input is detected, a DMAC
bus cycle is issued and DMA transfer effected, at the earliest, after three states. However, in burst
mode when single address operation is specified, a dummy cycle is inserted for the first bus cycle.
In this case, the actual data transfer starts from the second bus cycle. Data is transferred
continuously from the second bus cycle. The dummy cycle is not counted in the number of
transfer cycles, so there is no need to recognize the dummy cycle when setting the TCR.
DREQ sampling from the second time begins from the start of the transfer one bus cycle prior to
the DMAC transfer generated by the previous sampling.
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