SH7040 Datasheet, PDF (559/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Start Data
1 _{bit (ID2)}
Serial
data
0 D0 D1
Stop Start Data
MPB bit bit (data 2)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0 1 Idling
(marking)
MPB
MPIE
RDRF
RDR
value
ID1
ID2
Data2
RxI interrupt request
(multiprocessor
interrupt), MPIE = 0
RxI interrupt handler Station’s ID, so receiving MPIE
reads data in RDR
continues, with data bit is again
and clears RDRF to 0
received by the RxI
set to 1
interrupt processing routine
Example: Own ID matches data, 8-bit data with multiprocessor bit and one stop bit
Figure 14.15 Example of SCI Receive Operation (ID Matches)
14.3.4 Clock Synchronous Operation
In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full duplex communication is possible while
sharing the same clock. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 14.16 shows the general format in clock synchronous serial communication.
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