SH7040 Datasheet, PDF (632/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

17.3.2 CMCNT Count Timing
One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 17.3 shows the timing.
CK
Internal clock
CMCNT input
clock
CMCNT
N–1
17.4 Interrupts
N
Figure 17.3 Count Timing
N+1
17.4.1 Interrupt Sources and DTC Activation
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by using the interrupt controller settings. See section 6, Interrupt Controller (INTC), for
details.
Interrupt requests can also be used as data transfer controller (DTC) activating sources. In this
case, channel priorities are fixed. See section 8, Data Transfer Controller (DTC), for details.
17.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 17.4 shows
the CMF bit set timing.
594