SH7040 Datasheet, PDF (591/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10, and
CH2 = 0. Buffer operation timing is shown in figure 15.8.
ADF
ADST
Set to 1
by software
Cleared to 0
by software
Channel 0
Conver-
A/D
A/D
sion ^Sampling conver- ^Sampling conver- ^Sampling
standby
1
sion 1
3
sion 3
5
Conversion
standby
Sampling
2
A/D
conver-
sion 2
Sampling
4
A/D
conver-
sion 4
Channel 1 Conversion standby
Channel 2 ^{Conversion standby}
Channel 3 Conversion standby
ADDRA
Conver- Conver- Conver-
sion
sion
sion
result 1 result 2 result 3
Conver-
sion
result 4
ADDRB
Conver- Conver-
sion
sion
result 1 result 2
Conver-
sion
result 3
ADDRC
ADDRD
Figure 15.8 Buffer Operation Example (Select Scan Mode: Two-Stage One-Group
Operation, When CH2–CH0 = B'001)
Buffer-Only Operation: When performing conversion only on the analog input channels
specified by the BUFE1 and BUFE0 bits, select group mode, and you can select the ADF flag
setting conditions with the CH2–CH0 bits.
Table 15.4 shows conversion during buffer operation and ADF flag setting conditions. The ADF
flag is set at the point in the table when the final conversion has ended. In single mode, conversion
is halted after the ADF flag is set to 1. In scan mode, conversion continues, and the converted data
is stored in sequence in the buffer registers specified by the BUFE1 and BUFE0 bits.
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