SH7040 Datasheet, PDF (12/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
22.7.2 Program-
Verify Mode
Figure 22.13
Program/Program
Verify Flow
Page Description
706 Figure amended
Start
Set SWE bit in FLMCR1
Wait 10 µs
*5
Store 32-byte program data in
reprogram data area
*4
n=1
m=0
Write 32-byte data in reprogram data area _*1
in RAM to flash memory consecutively
Enable WDT
Set PSU1(2) bit in FLMCR1(2)
Wait 50 µs
*5
Set P1(2) bit in FLMCR1(2)
Wait 200 µs
Start of programming
*5
Clear P1(2) bit in FLMCR1(2)
End of programming
Wait 10 µs
*5
Clear PSU1(2) bit in FLMCR1(2)
Wait 10 µs
*5
Disable WDT
Set PV1(2) bit in FLMCR1(2)
Wait 4 µs
*5
Verify
Increment address
Dummy write of H'FF to verify address
Wait 2 µs
*5
Read verify data
*2
*3
Program data = verify data?
NG
OK
Reprogram data computation
*3
m=1
n←n+1
Transfer reprogram data to reprogram
data area
*4
NG
End of 32-byte
data verification?
OK
Clear PV1(2) bit in FLMCR1(2)
Wait 4 µs
flag = 0?
*5
NG
*5
n ≥ 1000 *5
NG
OK
Clear SWE bit in FLMCR1
OK
Clear SWE bit in FLMCR1
End of programming
Programming failure
Note *5 added.
*5 Make sure to set the wait times and repetitions as specified.
Programming may not complete correctly if values other than
the specified ones are used.