SH7040 Datasheet, PDF (129/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 5.5 Types of Resets
Type
Power-on reset
Manual reset
Conditions for Transition
to Reset Status
RES
MRES
Low
—
High
Low
CPU
Initialized
Initialized
Internal Status
On-Chip Peripheral Module
Initialized
Not initialized
5.2.1 Power-On Reset
When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES
pin should be kept at low for at least the duration of the oscillation settling time when applying
power or when in standby mode (when the clock circuit is halted) or at least 20 t_cyc (when the
clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip
peripheral modules are initialized. See Appendix C, Pin States, for the status of individual pins
during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3–I0) of
the status register (SR) are set to H'F (1111).
4. The values fetched from the exception processing vector table are set in the program counter
(PC) and SP and the program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
5.2.2 Manual Reset
When the RES pin is high and the MRES pin is driven low, the LSI does a manual reset. To
reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the
oscillation settling time when in standby mode (when the clock is halted) or at least 20 t_cyc when
the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-
chip peripheral modules are not initialized. Since the BSC is not affected, the DRAM refresh
control functions remain operational even when the manual reset status continues for a long period
of time. When the LSI enters manual reset status in the middle of a bus cycle, manual reset
exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort
bus cycles. However, the bus cycle ends once MRES is driven low. Hold at low level until manual
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