SH7040 Datasheet, PDF (386/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.4.8 Reset-Synchronized PWM Mode
In the reset-synchronized PWM mode, three-phase output of positive and negative PWM
waveforms that share a common wave transition point can be obtained using channels 3 and 4.
When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C,
TIOC4B, and TIOC4D pins become PWM output pins and TCNT3 becomes an upcounter.
Table 12.13 shows the PWM output pins used. Table 12.14 shows the settings of the registers.
Table 12.13 Output Pins for Reset-Synchronized PWM Mode
Channel
3
4
Output Pin
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Description
PWM output 1
PWM output 1' (negative-phase waveform of PWM output 1)
PWM output 2
PWM output 2' (negative-phase waveform of PWM output 2)
PWM output 3
PWM output 3' (negative-phase waveform of PWM output 3)
Table 12.14 Register Settings for Reset-Synchronized PWM Mode
Register Description of Contents
TCNT3 Initial setting of H'0000
TCNT4 Initial setting of H'0000
TGR3A Set count cycle for TCNT3
TGR3B Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins
TGR4A Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins
TGR4B Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins
Procedure for Selecting the Reset-Synchronized PWM Mode (Figure 12.35):
1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt TCNT3 and TCNT4. The reset-
synchronized PWM mode must be set up while TCNT3 and TCNT4 are halted.
2. Set bits TPSC2–TPSC0 and CKEG1 and CKEG0 in the TCR to select the counter clock and
clock edge for channel 3.
3. Set bits CCLR2–CCLR0 in the TCR3 to select TGRA compare-match as a counter clear
source.
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