SH7040 Datasheet, PDF (476/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

(24) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.120 shows an
explanatory diagram of the case where an error occurs in complementary PWM mode and
operation is restarted in reset-synchronous PWM mode.
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2
3
4
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8
9
10
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RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU) (1)
occurs (PORT) (0) (normal) (0)
(RPWM) (1) (MTU) (1)
MTU output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
PE9
PE11
High-Z
High-Z
High-Z
Figure 12.120 Error Occurrence in Complementary PWM Mode,
Recovery in Reset-Synchronous PWM Mode
1 to 10 are the same as in figure 12.116.
11. Set normal mode. (MTU output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling
with TOCR.
14. Set reset-synchronous PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU output with the PFC.
17. Operation is restarted by TSTR.
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