SH7040 Datasheet, PDF (489/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.11 Operation
12.11.1 Input Level Detection Operation
If the input conditions set by the ICSR occur on any of the POE pins, all high-current pins become
high-impedance state.
Falling Edge Detection: When a change from high to low level is input to the POE pins.
Low-Level Detection: Figure 12.126 shows the low-level detection operation. Sixteen continuous
low levels are sampled with the sampling clock established by the ICSR. If even one high level is
detected during this interval, the low level is not accepted.
CK
Sampling
clock
POE input
8/16/128 clock
cycles
PE9/TIOC3B
High-impedance
state^*
When low level is sampled
Flag set
at all points ¹
2
3
16 _{(POE received)}
When high level is sampled
at least once
1
2
13 Flag not set
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C/DACK0/AH,
PE15/TIOC4D/DACK1/IROOUT) also go to the high-impedance state at the same time.
Figure 12.126 Low-Level Detection Operation
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