SH7040 Datasheet, PDF (239/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.5.3 CS Assertion Extension
The timing diagram when setting CS assertion extension during address/data multiplex I/O space
access is shown in figure 10.19.
T_a1
T_a2
T_a3
T_a4
T_h
T₁
T₂
T_f
Address
CS3
AH
Read
RD
Data
WRxx
Write
Data
Address output
Address output
Data input
Data output
Figure 10.19 Wait Timing in Address/Data Multiplex I/O Space when CS Assertion
Extension is Set
10.6 Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data
conflicts with the next access. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the CSn signal once.
10.6.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read
cycles, waits are inserted so that the number of idle cycles specified by the IW31–IW00 bits of the
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