SH7040 Datasheet, PDF (400/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Register data updating
In complementary PWM mode, the buffer register is used to update the data in a compare
register. The update data can be written to the buffer register at any time. There are five PWM
duty and carrier cycle registers that have buffer registers and can be updated during operation.
There is a temporary register between each of these registers and its buffer register. When
subcounter TCNTS is not counting, if buffer register data is updated, the temporary register
value is also rewritten. Transfer is not performed from buffer registers to temporary registers
when TCNTS is counting; in this case, the value written to a buffer register is transferred after
TCNTS halts.
The temporary register value is transferred to the compare register at the data update timing set
with bits MD3–MD0 in the timer mode register (TMDR). Figure 12.42 shows an example of
data updating in complementary PWM mode. This example shows the mode in which data
updating is performed at both the counter crest and trough.
When rewriting buffer register data, a write to TGR4D must be performed at the end of the
update. Data transfer from the buffer registers to the temporary registers is performed
simultaneously for all five registers after the write to TGR4D.
A write to TGR4D must be performed after writing data to the registers to be updated, even
when not updating all five registers, or when updating the TGR4D data. In this case, the data
written to TGR4D should be the same as the data prior to the write operation.
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