SH7040 Datasheet, PDF (682/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

The IFCR is initialized to H'0000 by external power-on reset but is not initialized for manual
resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
IRQ
IRQ
IRQ
IRQ
MD3 MD2 MD1 MD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
• Bits 3 and 2—IRQOUT Mode 3, 2 (IRQMD3 and IRQMD2): These bits select the IRQOUT
pin function when the PDCRH1 bits 13 and 12 (PD30MD1, PD30MD0) are set to (1, 0). These
bit settings are effective only for the 144 pin version. Reads and writes are also possible in the
112-pin and 120-pin versions, but they have no effect on the pin functions.
Bit 3: IRQMD3
0
1
Bit 2: IRQMD2
0
1
0
1
Description
Interrupt request received output (initial value)
Refresh signal output
Interrupt request received, or refresh signal output
(which of the two is output depends on the operation
status at the time)
Always high level output
• Bits 1 and 0—IRQOUT Mode 1, 0 (IRQMD1 and IRQMD0): These bits select the IRQOUT
pin function when the PECR1 bits 1 and 0 (PE15MD1, PE15MD0) are set to (1, 1).
Bit 1: IRQMD1
0
1
Bit 0: IRQMD0
0
1
0
1
Description
Interrupt request received output (initial value)
Refresh signal output
Interrupt request received, or refresh signal output
(which of the two is output depends on the operation
status at the time)
Always high level output
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