SH7040 Datasheet, PDF (184/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Through DTC activation, a register information start address is read from the vector table, then
register information placed in memory space is read from that register information start address.
Always designate register information start addresses in multiples of four.
DTBR
Register information
start address
(upper 16 bits)
DTC vector table
DTC vector address
Register
information
start address
(lower 16 bits)
Memory space
Register
information
Figure 8.4 Correspondence between DTC Vector Address and Register Information
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