SH7040 Datasheet, PDF (578/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

15.2 Register Descriptions
15.2.1 A/D Data Registers A–H (ADDRA–ADDRH)
The ADDR are 16-bit read only registers for storing A/D conversion results. There are eight of
these registers, ADDRA through ADDRH.
The A/D converted data is 10-bit data which is sent to the ADDR for the corresponding converted
channel for storage. The lower 8 bits of the A/D converted data are transferred to and stored in the
lower byte (bits 7–0) of the ADDR, and the upper 2 bits are stored into the upper byte (bits 9, 8).
Bits 15–10 always read as 0. Data reads can be either byte or word. The upper 8 bits of the
converted data are transferred upon byte data reads. Additionally, buffered operation is possible by
combining ADDRA–ADDRD.
Table 15.3 shows the correspondence between the analog input channels and the ADDR.
The ADDR are initialized to H'0000 by power-on reset or in standby mode. Manual reset does not
initialize ADDR.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
AD9 AD8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
540