SH7040 Datasheet, PDF (219/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 3–2—DRAM Bus Width Specification (SZ1, SZ0): Specifies the DRAM space bus width.
Bit 3 (SZ1)
0
1
Bit 2 (SZ0)
0
1
Don’t care
Description
Byte (8 bits) (initial value)
Word (16 bits)
Longword (32 bits)
• Bits 1–0—DRAM Address Multiplex (AMX1–AMX0): Specifies the DRAM address
multiplex count.
Bit 1 (AMX1)
0
1
Bit 0 (AMX0)
0
1
0
1
Description
9 bit (initial value)
10 bit
11 bit
12 bit
10.2.6 Refresh Timer Control/Status Register (RTCSR)
RTCSR is a 16-bit read/write register that selects the refresh mode and the clock input to the
refresh timer counter (RTCNT), and controls compare match interrupts (CMI).
RTCSR is initialized by power-on resets and hardware standbys to H'0000, but is not initialized by
manual resets or software standbys.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
CMF
0
R/W
5
CMIE
0
R/W
4
CKS2
0
R/W
3
CKS1
0
R/W
2
CKS0
0
R/W
1
RFSH
0
R/W
0
RMD
0
R/W
• Bits 15–7—Reserved: These bits always read as 0. The write value should always be 0.
181