SH7040 Datasheet, PDF (198/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

9.4 Cautions on Use
9.4.1 Cache Initialization
Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to
all valid bits for all entries (256 times), that is,those in the address range H'FFFFF000–
H'FFFFF3FF.
Writes to the address array or data array by the CPU, DMAC, or DTC are not possible while the
cache is enabled. For reads, undefined values will be read out.
9.4.2 Forced Access to Address Array and Data Array
While the cache is enabled, it is not possible to write to the address array or data array via the
CPU, DMAC, or DTC, and a read will return an undefined value. The cache must be disabled
before making a forced access to the address array or data array.
9.4.3 Cache Miss Penalty and Cache Fill Timing
When a cache miss occurs, a single idle cycle is generated as a penalty immediately before the
cache fill (access from external memory in the event of a cache miss), as shown in figure 9.5.
However, in the case of consecutive cache misses, idle cycles are not generated for the second and
subsequent cache misses, as shown in figure 9.6.
As the timing for a cache fill from normal space, the CS assert period immediately before the end
of the bus cycle (or the last bus cycle when two or four bus cycles are generated, such as in a word
access to 8-bit space) is extended by an additional cycle, as shown in figures 9.5 and 9.6.
Similarly, as the timing for a cache fill from DRAM space, the RAS assert period immediately
before the end of the bus cycle is extended by an additional cycle. In RAS down mode, the next
bus cycle is delayed by one cycle as shown in figure 9.8.
160