SH7040 Datasheet, PDF (796/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 25.7 Bus Timing (Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_CC = V_CC ±
10%, AV_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V, Ta = – 20 to +75°C)
Item
Symbol Min
Max Unit Figure
Write address setup time
t _AS
Write address hold time
t _WR
Write data hold time
t _WRH
Read/write strobe delay time 1 t_RWD1
Read/write strobe delay time 2 t_RWD2
High-speed page mode CAS t_CP
precharge time
0
5
0
2^*3
2^*3
t_cyc – 25
— ns 25.8–25.9
— ns 25.8, 25.9, 25.19
— ns
18 ns 25.11–25.16
18 ns
— ns 25.16
RAS precharge time
CAS setup time
AH delay time 1
AH delay time 2
Multiplex address delay time
Multiplex address hold time
DACK delay time
t _RP
t _CSR
t _AHD1
t _AHD2
t _MAD
t _MAH
t _DACKD1
t_cyc × (TPC + 1.5) – 15 —
10
—
2^*3
18
2^*3
18
2^*3
18
0
—
2^*3
21
ns 25.11–25.16
ns 25.17, 25.18
ns 25.19
ns
ns
ns
ns 25.8, 25.9, 25.11–
25.16, 25.19
Notes: n is the number of waits. m is 0 when the number of DRAM write cycle waits is 0, and 1
otherwise. RCD is the set value of the RCD bit in DCR. TPC is the set value of the TPC bit
in DCR.
*1 If the access time is satisfied, t_RDS need not be satisfied.
*2 t_WDH (max) is a reference value.
*3 The delay time Min values are reference values (typ).
*4 t_RDS is a reference value.
*5 When 28.7MHz, tASR=0ns (min)
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