SH7040 Datasheet, PDF (698/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

19.5.3 Port D Data Register L (PDDRL)
PDDRL is a 16-bit read/write register that stores data for port D. The bits PD15DR–PD0DR
correspond to the PD15/D15–PD0/D0 pins. When the pins are used as ordinary outputs, they will
output whatever value is written in the PDDRL; when PDDRL is read, the register value will be
read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather
than the register value is read directly when PDDRL is read. When a value is written to PDDRL,
that value can be written into PDDRL, but it will not affect the pin status. Table 19.14 shows the
read/write operations of the port D data register.
PDDRL is initialized by an external power-on reset. However, PDDRL is not initialized for a
manual reset, reset by WDT, standby mode, or sleep mode.
Bit: 15
14
13
12
11
10
9
8
PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 19.14 Read/Write Operation of the Port D Data Register (PDDR)
PDIOR
0
1
Pin Status
Read
Ordinary input Pin status
Other function Pin status
Ordinary output PDDR value
Other function PDDR value
Write
Can write to PDDR, but it has no effect on pin status
Can write to PDDR, but it has no effect on pin status
Value written is output by pin
Can write to PDDR, but it has no effect on pin status
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