SH7040 Datasheet, PDF (123/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

External circuitry such as that shown in figure 4.6 is recommended around the PLL.
PLLCAP
PLLV_CC
PLLV_SS
R1: 3 kΩ
C1: 470 pF
Rp: 200 Ω
CPB: 0.1 µF^*
V_CC
CB: 0.1 µF^*
V_SS
Note: * CB and CPB are laminated ceramic capacitors
(Recommended values)
Figure 4.6 Cautions for Use of PLL Oscillator Circuit
Place oscillation stabilization capacitor C1 and resistor R1 near the PLLCAP pin, and ensure that
these lines do not cross any other signal lines. Supply the C1 ground from PLLV_SS.
Also, separate PLLV_CC and PLLV_SS, and the other V_CC and V_SS pins, from the board power supply
source, and be sure to insert bypass capacitors CPB and CB close to the pins.
If V_CC and PLLV_CC are both 3.3 V ± 0.3 V, it is recommended that Rp be set to 0 Ω.
4.5.3 Spread Spectrum Clock Generator Usage Notes
The following points should be borne in mind when using a spread spectrum clock generator as an
external oscillator in order to reduce radiation noise.
• Set the center frequency and the spread amplitude such that the internal clock does not exceed
the maximum frequency during spread spectrum operation.
• Using a spread spectrum clock generator may trigger the oscillator halt function described in
section 4.4. If the system configuration is such that this function will cause problems, a spread
spectrum clock generator should not be used.
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