SH7040 Datasheet, PDF (328/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.2.3 Timer I/O Control Register (TIOR)
The TIOR is a register that controls the TGR. The MTU has eight TIOR registers, two each for
channels 0, 3, and 4, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on
reset or the standby mode. Manual reset does not initialize TIOR.
Channels 0, 3, 4: TIOR0H, TIOR3H, TIOR4H
Channels 1, 2: TIOR1, TIOR2:
Bit:
Initial value:
R/W:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
• Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGRB register function.
• Bits 3–0—I/O Control A3–B0 (IOA3–IOA0): These bits set the TGRA register function.
Channels 0, 3, 4: TIOR0L, TIOR3L, TIOR4L:
Bit: 7
6
5
4
3
2
1
0
IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: When the TGRC or TGRD registers are set for buffer operation, these settings become
ineffective and the operation is as a buffer register.
• Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGRD register function.
• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGRC register function.
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