SH7040 Datasheet, PDF (279/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

1st, 2nd bus cycles
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The SAR3 value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.
When external connection data bus is 16 bits, two bus cycles are required.
3rd bus cycle
DMAC
SAR3
DAR3
Temporary
buffer
Data
buffer
Memory
Transfer source
module
Transfer destination
module
The value in the temporary buffer is taken as the address, and data is read from the
transfer source module to the data buffer.
4th bus cycle
DMAC
SAR3
DAR3
Temporary
buffer
Data
buffer
Memory
Transfer source
module
Transfer destination
module
The DAR3 value is taken as the address, and the value in the data buffer is written to the
transfer destination module.
Note: Memory, transfer source, and transfer destination modules are shown here.
In practice, connection can be made anywhere there is address space.
Figure 11.9 Dual Address Mode and Indirect Address Operation
(When External Memory Space is 16 bits)
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