SH7040 Datasheet, PDF (539/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

14.3 Operation
14.3.1 Overview
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission
format are selected in the serial mode register (SMR), as shown in table 14.8. The SCI clock
source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits
in the serial control register (SCR), as shown in table 14.9.
Asynchronous Mode:
• Data length is selectable: seven or eight bits.
• Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits).
These selections determine the transmit/receive format and character length.
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors
(ORER), and the break state.
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and can output a clock with a frequency matching the bit rate.
 When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Clock Synchronous Mode:
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and outputs a synchronous clock signal to external devices.
 When an external clock is selected, the SCI operates on the input synchronous clock. The
on-chip baud rate generator is not used.
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