SH7040 Datasheet, PDF (138/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
UBC
DMAC
MTU
CMT
SCI
A/D
DTC
WDT
BSC
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
CPU/
DTC
request
judg-
ment
Priority
ranking
judg-
ment
Com-
parator
ICR
IPR
ISR
IPRA–IPRH
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTER
DTC
Module bus
Bus
interface
INTC
UBC: User break controller
I/O: I/O port (port output control section)
DMAC: Direct memory access controller
ICR: Interrupt control register
MTU: Multifunction timer pulse unit
ISR: IRQ ststus register
CMT: Compare match timer
DTER: DTC enable register
SCI: Serial communication interface IPRA–IPRH: Interrupt priority level setting
A/D: A/D converter
registers A to H
DTC: Data transfer controller
SR: Status register
WDT: Watchdog timer
BSC: Bus state controller (DRAM
refresh control section)
Figure 6.1 INTC Block Diagram
100