SH7040 Datasheet, PDF (182/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Start
Initial settings
DTMR, DTCR, DTIAR, DTSAR, DTDAR
No
NMIF = AE = 0?
Yes
Transfer request
No
generated?
Yes
DTC vector read
Transfer information read
DTCRA = DTCRA – 1 (normal/block transfer mode)
DTCRAL = DTCRAL – 1 (repeat mode)
Transfer (1 transfer unit)
DTSAR, DTDAR update
DTCRB = DTCRB – 1 (block transfer mode)
NMIF • NMIM
No
+ AE = 1?
Yes
Transfer information write
Block
transfer mode and
Yes
DTCRB ≠ 0?
No
Transfer information write
NMI or address error
No
CHNE = 0?
Yes
CPU interrupt request
When DISEL = 1 or DTCRA = 0 (normal/block transfer mode)
When DISEL = 1 (repeat transfer mode)
End
Figure 8.2 DTC Operation Flowchart
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