SH7040 Datasheet, PDF (112/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception processing vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the power-down state. This state has two
modes: sleep mode and standby mode.
Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device
that has requested them.
2.5.2 Power-Down State
Besides the ordinary program execution states, the CPU also has a power-down state in which
CPU operation halts, lowering power consumption. There are two power-down state modes: sleep
mode and standby mode.
Sleep Mode: When standby bit SBY (in the standby control register SBYCR) is cleared to 0 and a
SLEEP instruction executed, the CPU moves from program execution state to sleep mode. In the
sleep mode, the CPU halts and the contents of its internal registers and the data in on-chip cache
(or on-chip RAM) is maintained. The on-chip peripheral modules other than the CPU do not halt
in the sleep mode.
To return from sleep mode, use a reset (power-on or manual), any interrupt, or a DMA address
error; the CPU returns to the ordinary program execution state through the exception processing
state.
Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby control
register SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip
peripheral module, and oscillator functions are halted. However, when entering standby mode, the
DMA master enable bit of the DMAC should be set to 0. If multiplication-related instructions are
being executed at the time of entry into standby mode, the values of MACH and MACL will
become undefined.
To return from standby mode, use a reset (power-on or manual) or an NMI interrupt. For resets,
the CPU returns to ordinary program execution state through the exception processing state when
placed in a reset state for the duration of the oscillator stabilization time. For NMI interrupts, the
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