SH7040 Datasheet, PDF (567/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Error handling
Overrun error processing
Clear ORER bit of SSR to 0
End
Figure 14.21 Sample Flowchart for Serial Receiving (2)
Figure 14.22 shows an example of the SCI receive operation.
Transfer direction
Synchroni-
zation clock
Serial
data
Bit 7 Bit 0
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
RDRF
ORER
RxI request Read data with RxI
interrupt processing
routine and clear
RDRF bit to 0
1 frame
RxI request
ERI interrupt
request generated
by overrun error
Figure 14.22 Example of SCI Receive Operation
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the
data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the
RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If
the check does not pass (receive error), the SCI operates as indicated in table 14.11 and no
further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set
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