SH7040 Datasheet, PDF (188/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

The total transfer count is specified between 1 and 256. When the specified number of transfers
ends, the address register of the designated repeat area is returned to its initial state and the transfer
is repeated. Other address registers are consecutively incremented, decremented, or remain fixed.
While DISEL = 0, no interrupt request is made to the CPU, even if the transfer with DTCRAL = 1
ends.
Pulses for driving the stepping motor can be output. Table 8.4 shows the register functions for
repeat mode.
Table 8.4 Repeat Mode Register Functions
Register
DTMR
DTCRAH
DTCRAL
DTIAR
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
maintenance
Transfer count
Initial address
Transfer source
address
Transfer destination
address
Values Written Back upon a
Transfer Information Write
When DTCRA is
other than 1
When DTCRA is 1
DTMR
DTMR
DTCRAH
DTCRAH
DTCRAL – 1
(Not written back)
Increment/decrement/
fixed
Increment/decrement/
fixed
DTCRAH
(Not written back)
(DTS = 0) Increment/
decrement/ fixed
(DTS = 1) DTIAR
(DTS = 0) DTIAR
(DTS = 1) Increment/
decrement/ fixed
8.3.7 Block Transfer Mode
Performs the transfer of one block for each one activation. Either the transfer source or transfer
destination is designated as the block area.
The block length is specified between 1 and 65536. When a 1-block transfers ends, the address
register of the designated block area is returned to its initial state. Other address registers are
consecutively incremented, decremented, or remain fixed. The block transfer count is 1 to 65536.
An interrupt request is generated to the CPU when the transfer with DTCRA = 1 ends.
A/D converter group mode transfers and phase compensation PWM data transfers are possible.
Table 8.5 shows the register functions for block transfer mode.
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