SH7040 Datasheet, PDF (353/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Counter Start
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Channel
Channel 4 (TCNT4)
Channel 3 (TCNT3)
Channel 2 (TCNT2)
Channel 1 (TCNT1)
Channel 0 (TCNT0)
Bit n: SYNCn
Description
0
Timer counter (TCNTn) independent operation (initial value)
(TCNTn preset/clear unrelated to other channels)
1
Timer counter synchronous operation^*1
TCNTn synchronous preset/ synchronous clear^*2 possible
Notes: n = 4 to 0. However, SYNC4 is bit 7, SYNC3 is bit 6.
*1 Minimum of two channel SYNC bits must be set to 1 for synchronous operation.
*2 TCNT counter clear sources (CCLR2–CCLR0 bits of the TCR register) must be set in
addition to the SYNC bit in order to have clear synchronization.
• Bits 5–3—Reserved: These bits always read as 0. The write value should always be 0.
12.2.10 Timer Output Master Enable Register (TOER)
The timer output master enable register (TOER) enables/disables output settings for output pins
TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly
if the TOER bits have not been set. Set TOER of CH3 and CH2 prior to setting TIOR of CH3 and
CH4. The TOER is an 8-bit read/write register. The register is initialized to H'C0 by a power-on
reset or in standby mode. Manual reset does not initialize TOER.
Bit: 7
—
Initial value: 1
R/W: R
6
5
4
3
2
1
0
— OE4D OE4C OE3D OE4B OE4A OE3B
1
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
• Bits 7–6—Reserved: These bits always read as 1. The write value should always be 1.
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