SH7040 Datasheet, PDF (210/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size when A1LG =
0.
Bit 1 (A1SZ)
Description
0
Byte (8 bit) size
1
Word (16 bit) size (initial value)
Note: This bit is ignored when A1LG = 1; CS1 space bus size becomes longword (32 bit).
• Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size when A0LG =
0.
Bit 0 (A0SZ)
Description
0
Byte (8 bit) size
1
Word (16 bit) size (initial value)
Note:
A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode,
the CS0 space bus size is specified by the mode pin. However, even in on-chip ROM
effective mode, this bit is ignored when A0LG = 1; CS0 space bus size becomes longword
(32 bit).
10.2.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert
extension of each CS space.
BCR2 is initialized by power-on resets to H'FFFF, but is not initialized by manual resets or
software standbys.
Bit:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
1
R/W
13
IW21
1
R/W
12
IW20
1
R/W
11
IW11
1
R/W
10
IW10
1
R/W
9
IW01
1
R/W
8
IW00
1
R/W
Bit:
Initial value:
R/W:
7
CW3
1
R/W
6
CW2
1
R/W
5
CW1
1
R/W
4
CW0
1
R/W
3
SW3
1
R/W
2
SW2
1
R/W
1
SW1
1
R/W
0
SW0
1
R/W
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