SH7040 Datasheet, PDF (552/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 14.8.
Clock: See the description in the asynchronous mode section.
Transmitting
processor
Receiving
processor A
(ID = 01)
Serial communication line
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID-transmit cycle:
receiving processor address
Data-transmit cycle:
data sent to receiving
processor specified by ID
MPB: Multiprocessor bit
Example: Sending data H'AA to receiving processor A
Figure 14.10 Communication among Processors Using Multiprocessor Format
Transmitting Multiprocessor Serial Data: Figure 14.11 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the
numbers in the flowchart):
1. SCI initialization: Set the TxD pin using the PFC.
2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC or the DTC is
started by a transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is
checked and cleared automatically.
4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then
clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
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