SH7040 Datasheet, PDF (795/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

25.3.3 Bus Timing
Table 25.6 Bus Timing (Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_CC = V_CC ±
10%, AV_ref = 4.5 V – AV_CC , V_SS = AV_SS = 0 V, Ta = – 20 to +75°C)
Item
Address delay time
CS delay time 1
CS delay time 2
Read strobe delay time 1
Read strobe delay time 2
Read data setup time
Read data hold time
Write strobe delay time 1
Write strobe delay time 2
Write data delay time
Write data hold time
WAIT setup time
WAIT hold time
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
Read data access time
Access time from read strobe
Access time from column
address
Access time from RAS
Access time from CAS
Row address hold time
Row address setup time
Data input setup time
Data input hold time
Symbol Min
t _AD
2^*3
t _CSD1
t _CSD2
t _RSD1
t _RSD2
t _RDS ^{* 4}
t _RDH
t _WSD1
t _WSD2
t _WDD
t _WDH
t _WTS
t _WTH
t _RASD1
t _RASD2
t _CASD1
t _CASD2
t _ACC ^{* 1}
t
*¹
OE
t
*
AA
1
2^*3
2^*3
2^*3
2^*3
15
0
2^*3
2^*3
—
0
15
0
2^*3
2^*3
2^*3
2^*3
t_cyc × (n + 2) – 40
t_cyc × (n + 1.5) – 40
t_cyc × (n + 2) – 40
Max Unit Figure
18 ns 25.8, 25.9,
25.11–25.16,
25.19
21 ns 25.8, 25.9, 25.19
21 ns
18 ns 25.8, 25.9,
18 ns ^{25.11–25.16,}
25.19
— ns
— ns
18 ns
18 ns
35 ns
10^*2 ns
— ns 25.10, 25.15,
— ns ^25.19
18 ns 25.11–25.18
18 ns
18 ns
18 ns
— ns 25.8, 25.9
— ns
— ns 25.11–25.16
t _RAC ^{* 1}
t _CAC ^{* 1}
t _RAH
t
*⁵
ASR
t _DS
t _DH
t_cyc × (n + RCD + 2.5) – 40 — ns
t_cyc × (n + 1) – 40
— ns
t_cyc × (RCD + 0.5) – 15 — ns
t_cyc × 0.5–17.5
— ns
t_cyc × (m + 0.5) – 25
— ns
20
— ns
757