SH7040 Datasheet, PDF(410/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (410/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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â¢ Counter clearing by another channel

In complementary PWM mode, by setting a mode for synchronization with another channel by

means of the timer synchro register (TSYR), and selecting synchronous clearing with bits

CCLR2âCCLR0 in the timer control register (TCR), it is possible to have TCNT3, TCNT4,

and TCNTS cleared by another channel.

Figure 12.54 illustrates the operation.

Use of this function enables counter clearing and restarting to be performed by means of an

external signal.

TGR3A

TCDR

TCNTS

TCNT3

TCNT4

TDDR

H'0000

Channel 1

input capture A

TCNT1

Synchronous counter clearing by channel 1 input capture A

Figure 12.54 Counter Clearing Synchronized with Another Channel

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