SH7040 Datasheet, PDF (280/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

CK
A21–A0
CSn
D15–D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
RD
WRH,
WRL
Transfer
source
address (H)
Transfer
source
address (L)
NOP
Indirect
address
Transfer
destination
address
Indirect
address (H)
Indirect
address (L)
Transfer source
address ^*1
NOP
Indirect address ^*2
Transfer
data
Transfer
data
Indirect
address
Transfer Transfer
data
data
Indirect
address
Transfer
data
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
Data
write cycle
(3rd)
(4th)
Notes: External memory space has 16-bit width.
*1 The internal address bus is controlled by the port and does not change.
*2 DMAC does not fetch value until 32-bit data is read from the internal data
bus.
Figure 11.10 Dual Address Mode and Indirect Address Transfer Timing Example 1
(External Memory Space to External Memory Space)
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