SH7040 Datasheet, PDF (824/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

26.3.2 Control Signal Timing
Table 26.5 Control Signal Timing (Conditions: V_CC = 3.0^*1 to 3.6V, AV_CC = 3.0^*1 to 3.6V,
AV_CC = V_CC ± 10%, AV_ref = 3.0^*1 to AV_CC, V_SS = AV_SS = 0V, T_a = –20 to +75°C)
Item
Symbol Min
Max
Unit
Figure
RES rise/fall
RES pulse width
MRES pulse width
t , _RESr t_RESf —
t _RESW
20
t _MRESW
20
200
ns
—
t _cyc
—
t _cyc
26.4
NMI rise/fall
RES setup time^*1
MRES setup time^*1
t , _NMIr t_NMIf —
200
ns
t _RESS
100
—
ns
t _MRESS
100
—
ns
26.5
26.4
26.5
NMI setup time (during edge detection)
t _NMIS
100
—
ns
IRQ7–IRQ0 setup time (edge detection)^*2 t_IRQES
100
—
ns
IRQ7–IRQ0 setup time (level detection)^*2 t_IRQLS
100
—
ns
NMI hold time
IRQ7–IRQ0 hold time
IRQOUT output delay time
t _NMIH
50
—
ns
26.5
t _IRQEH
50
—
ns
t _IRQOD
—
50
ns
26.6
Bus request setup time
t _BRQS
35
—
ns
26.7
Bus acknowledge delay time 1
t _BACKD1
—
35
ns
Bus acknowledge delay time 2
t _BACKD2
—
35
ns
Bus three state delay time
t _BZD
—
35
ns
Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.
*2 The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but
when the setup times shown here are provided, the signals are considered to have
produced changes at clock rise (for RES, MRES, BREQ) or clock fall (for NMI and
IRQ7–IRQ0). If the setup times are not provided, recognition is delayed until the next
clock rise or fall.
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