SH7040 Datasheet, PDF (16/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
25.4 A/D Converter
Characteristics
Table 25.16 A/D
Converter Timing (A
mask)
Page
779
Description
Table amended
Non-linearity error ^*
Offset error^*
Full scale error^*
Quantize error^*
26.2 DC
Characteristics
Table 26.2 DC
Characteristics
782
783
Table amended
Schmitt PA2, PA5, PA6–
trigger input PA9,
V_T+ – V_T^–
voltage PE0–PE15
V_CC×
0.07
——
Table amended
Analog
supply
current
AI _CC
—
AI _ref
—
48
0.5 1^*3
V VT⁺ ≥ V_CC× 0.9V (min)
VT^– ≤ V_CC× 0.2V (max)
mA f = 16.7MHz
mA QFP144 version only
26.3.2 Control
786
Signal Timing
Table 26.5 Control
Signal Timing
26.3.3 Bus Timing 795
Figure 26.12 DRAM
Cycle (Normal Mode,
1 Wait, TPC = 0,
RCD = 0)
*3 2 mA in the A mask version of MASK products.
Note amended
Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.
*2 The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals
are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to
have produced changes at clock rise (for RES, MRES,
BREQ) or clock fall (for NMI and IRQ7–IRQ0). If the
setup times are not provided, recognition is delayed until
the next clock rise or fall.
Figure amended
Tcw1
Tc2
Column address
t_CASD1
t_CAC
t_AA
t_RAC
t_RDS