SH7040 Datasheet, PDF (191/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

8.3.10 DTC Usage Procedure
The procedure for DTC interrupt activation is as follows:
1. Transfer data (DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR) is located in
memory space.
2. Establish the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. The DTC is activated when an interrupt source occurs.
5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER
is not. When interrupts are requested, the interrupt source is not cleared, but the DTER is.
6. Interrupt sources are cleared within the CPU interrupt routine. When doing continuous DTC
data transfers, set the DTER to 1.
The procedure for DTC software activation is as follows:
1. Transfer data (DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR) is located in
memory space.
2. Establish the register information start address with DTBR and the DTC vector table.
3. Confirm that the SWDTE bit of the DTCSR is 0. When the SWDTE bit is 1, the DTC is
already being driven by software.
4. Write a 1 to the SWDTE bit and a vector number to the DTVEC (byte data).
5. When SWDTCE interrupt requests are not made to the CPU, the SWDTE bit is cleared. When
interrupts are requested, the SWDTE bit is maintained as a 1.
6. The SWDTE bit is cleared to 0 within the CPU interrupt routine. For continuous DTC data
transfers, set the SWDTE to 1.
8.3.11 DTC Use Example
The following is a DTC use example of a 128-byte data reception by the SCI:
1. The settings are: DTMR source address fixed (SM1 = 0), destination address incremented
(DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), byte size (SZ1 = SZ0 = 0), one
transfer per activating source (CHNE = 0), and a CPU interrupt request after the designated
number of data transfers (DISEL = 0). 128 (H'0080) is set in DTCRA, the RDR address of the
SCI is set in DTSAR, and the start address of the RAM storing the receive data is set in
DTDAR.
2. Establish the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. Set the SCI to a specific receive mode and enable RxI interrupts.
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