SH7040 Datasheet, PDF (95/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.9 Instruction Formats (cont)
Instruction Formats
nm format
15
0
xxxx nnnn mmmm xxxx
Source Operand Destination
Operand
mmmm: Direct
register
nnnn: Direct
register
mmmm: Direct
register
nnnn: Indirect
register
Example
ADD Rm,Rn
MOV.L Rm,@Rn
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
xxxx xxxx
0
nnnn dddd
mmmm: Indirect
post-increment
register (multiply/
accumulate)
nnnn^*: Indirect
post-increment
register (multiply/
accumulate)
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
mmmmdddd:
indirect register
with
displacement
R0 (Direct
register)
MACH, MACL
nnnn: Direct
register
nnnn: Indirect pre-
decrement
register
nnnn: Indirect
indexed register
R0 (Direct
register)
nnnndddd:
Indirect register
with displacement
MAC.W
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
MOV.B
@(disp,Rm),R0
MOV.B
R0,@(disp,Rn)
nmd format
15
0
xxxx nnnn mmmm dddd
mmmm: Direct
register
nnnndddd: Indirect MOV.L
register with
Rm,@(disp,Rn)
displacement
mmmmdddd:
Indirect register
with
displacement
nnnn: Direct
register
Note: * In multiply/accumulate instructions, nnnn is the source register.
MOV.L
@(disp,Rm),Rn
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