SH7040 Datasheet, PDF (267/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Figure 11.2 is a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?^*1
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR, and DAR
updated
*2
Bus mode,
*3
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer aborted
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer ends
Normal end
Notes: *1
*2
*3
In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
DREQ = level detection in burst mode (external request), or cycle-steal
mode.
DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
Figure 11.2 DMAC Transfer Flowchart
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