SH7040 Datasheet, PDF (349/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 2—Input Capture/Output Compare Flag C (TGFC): This status flag indicates the
occurrence of a channel 0, 3, or 4 TGRC register input capture or compare-match.
This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always
be 0.
Bit 2: TGFC
0
1
Description
Clear condition:
With TGFC = 1, a 0 write to TGFC following a read (Cleared by DTC
transfer due to TGFC) (initial value)
Set conditions:
• When TGRC is functioning as an output compare register
(TCNT = TGRC)
• When TGRC is functioning as input capture (the TCNT value is sent
to TGRC by the input capture signal)
• Bit 1—Input Capture/Output Compare Flag B (TGFB): This status flag indicates the
occurrence of a TGRB register input capture or compare-match.
Bit 1: TGFB
0
1
Description
Clear condition: With TGFB = 1, a 0 write to TGFB following a read
(Cleared by DTC transfer due to TGFB) (initial value)
Set conditions:
• When TGRB is functioning as an output compare register
(TCNT = TGRB)
• When TGRB is functioning as input capture (the TCNT value is sent
to TGRB by the input capture signal)
• Bit 0—Input Capture/Output Compare Flag A (TGFA): This status flag indicates the
occurrence of a TGRA register input capture or compare-match.
Bit 0: TGFA
0
1
Description
Clear condition: With TGFA = 1, a 0 write to TGFA following a read
(Cleared by DMAC transfer due to TGFA) (initial value)
Set conditions:
• When TGRA is functioning as an output compare register
(TCNT = TGRA)
• When TGRA is functioning as input capture (the TCNT value is sent
to TGRA by the input capture signal)
311