SH7040 Datasheet, PDF(266/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (266/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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â¢ Bit 0âDMAC Master Enable (DME): This bit enables activation of the entire DMAC. When

the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel

is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are

suspended.

Even when the DME bit is set, when the TE bit of the CHCR is 1, or its DE bit is 0, transfer is

disabled in the case of an NMI of the DMAOR or when AE = 1.

Bit 0: DME

0

1

Description

Disable operation on all channels (initial value)

Enable operation on all channels

11.3 Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the

predetermined channel priority order; when the transfer end conditions are satisfied, it ends the

transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip

peripheral module request. Transfer can be in either the single address mode or the dual address

mode, and dual address mode can be either direct or indirect address transfer mode. The bus mode

can be either burst or cycle steal.

11.3.1 DMA Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA

transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation

register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according

to the following procedure:

1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,

AE = 0).

2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer

unit of data (determined by TS0 and TS1 setting). For an auto-request, the transfer begins

automatically when the DE bit and DME bit are set to 1. The DMATCR value will be

decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus

mode.

3. When the specified number of transfers have been completed (when DMATCR reaches 0), the

transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent

to the CPU.

4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is

aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the

DMAOR are changed to 0.

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