SH7040 Datasheet, PDF (110/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.17 System Control Instructions (cont)
Instruction
Instruction Code
Operation
Exec.
Cycles T Bit
STS.L MACH,@–Rn 0100nnnn00000010
Rn–4 → Rn, MACH → (Rn) 1
—
STS.L MACL,@–Rn 0100nnnn00010010
Rn–4 → Rn, MACL → (Rn) 1
—
STS.L PR,@–Rn
0100nnnn00100010
Rn–4 → Rn, PR → (Rn)
1
—
TRAPA #imm
11000011iiiiiiii
PC/SR → stack area,
8
—
(imm × 4 + VBR) → PC
Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles
shown in the table are minimums. The actual number of cycles may be increased when
(1) contention occurs between instruction fetches and data access, or (2) when the
destination register of the load instruction (memory → register) and the register used by
the next instruction are the same.
2.5 Processing States
2.5.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.6 shows the transitions between the states.
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