SH7040 Datasheet, PDF (369/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Procedure for Selecting the Synchronizing Mode (Figure 12.15):
1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel
in the synchronizing mode.
2. When a value is written in the TCNT in any of the synchronized channels, the same value is
simultaneously written in the TCNT in the other channels.
3. Set the counter to clear with output compare/input capture using bits CCLR2–CCLR0 in the
TCR.
4. Set the counter clear source to synchronized clear using the CCLR2–CCLR0 bits of the TCR.
5. Set the CST bits for the corresponding channels in the TSTR to 1 to start counting in the
TCNT.
Select
synchronizing mode
Set synchronizing 1
mode
Synchronized preset
Set TCNT
2
Synchronized clear
Channel that
No
generated clear
source?
Yes
Select counter
3
clear source
Start counting
5
Set counter
4
synchronous clear
Start counting
5
Synchronized preset
Counter clear
Synchronized clear
Figure 12.15 Procedure for Selecting Synchronizing Operation
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