SH7040 Datasheet, PDF (691/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

19.3.2 Port B Data Register (PBDR)
PBDR is a 16-bit read/write register that stores data for port B. The bits PB9DR–PB0DR
correspond to the PB9/IRQ7/A21/ADTRG–PB0/A16 pins. When the pins are used as ordinary
outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register
value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin
status rather than the register value is read directly when PBDR is read. When a value is written to
PBDR, that value can be written into PBDR, but it will not affect the pin status. Table 19.7 shows
the read/write operations of the port B data register.
PBDR is initialized by an external power-on reset. However, PBDR is not initialized for a manual
reset, reset by WDT, standby mode, or sleep mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
— PB9DR PB8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 19.7 Read/Write Operation of the Port B Data Register (PBDR)
PBIOR
0
1
Pin Status
Ordinary input
Other function
Ordinary output
Other function
Read
Pin status
Pin status
PBDR value
PBDR value
Write
Can write to PBDR, but it has no effect on pin status
Can write to PBDR, but it has no effect on pin status
Value written is output by pin
Can write to PBDR, but it has no effect on pin status
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