SH7040 Datasheet, PDF(435/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (435/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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12.7.9 Contention between TGR Write and Compare Match

If a compare-match occurs in the T2 state of the TGR write cycle, data is written to the TGR and a

compare-match signal is issued (figure 12.84).

TGR write cycle

T1

T2

Ï

Address

TGR address

Write signal

Compare

match signal

TCNT

N

N+1

TGR

N

M

TGR write data

Figure 12.84 TGR Write and Compare Match Contention

12.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs

during TCNT1 count (during a TCNT2 overflow/underflow) in the T2 state of the TCNT2 write

cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if

there is match with TGR1A or TGR1B and the TCNT1 value, a compare signal is issued. The

timing is shown in figure 12.85.

For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT

clearing.

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