SH7040 Datasheet, PDF (744/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Start
Set SWE bit in FLMCR1
Wait 10 µs
*5
Store 32-byte program data in
reprogram data area
*4
n=1
RAM
Program data storage
area (32 bytes)
Reprogram data storage
area (32 bytes)
m=0
Write 32-byte data in reprogram data area _*1
in RAM to flash memory consecutively
Enable WDT
Set PSU1(2) bit in FLMCR1(2)
Wait 50 µs
*5
Set P1(2) bit in FLMCR1(2)
Wait 200 µs
Start of programming
*5
Clear P1(2) bit in FLMCR1(2)
End of programming
Wait 10 µs
*5
Clear PSU1(2) bit in FLMCR1(2)
Wait 10 µs
*5
Disable WDT
Set PV1(2) bit in FLMCR1(2)
Wait 4 µs
*5
Verify
Increment address
Dummy write of H'FF to verify address
Wait 2 µs
*5
Read verify data
*2
*3
Program data = verify data?
NG
OK
Reprogram data computation
*3
m=1
Transfer reprogram data to reprogram
data area
*4
n←n+1
NG
Notes: *1 Data transfer is performed by byte transfer. The lower
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
*2 Verify data is read in 32-bit (longword) units.
*3 Even bits for which programming has been completed in a
32-byte programming loop will be subjected to additional
programming if they fail the subsequent verify operation.
*4 A 32-byte area for storing program data and a 32-byte area for
storing reprogram data are required in RAM. The contents of
the latter are rewritten according to the progress of the
programming operation.
*5 Make sure to set the wait times and repetitions as specified.
Programming may not complete correctly if values other than
the specified ones are used.
End of 32-byte
data verification?
OK
Clear PV1(2) bit in FLMCR1(2)
Wait 4 µs
flag = 0?
OK
Clear SWE bit in FLMCR1
*5
NG
*5
NG
n ≥ 1000 *5
OK
Clear SWE bit in FLMCR1
End of programming
Programming failure
Note: The memory erased state is 1. Programming is performed on 0 data.
Write data (D) Verify data (V) Rewrite data (X)
Comment
0
0
1
Programming completed
0
1
0
Programming incomplete; reprogram
1
0
1
1
1
1
Still in erased state; no action
Figure 22.13 Program/Program Verify Flow
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