SH7040 Datasheet, PDF (565/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Receiving Serial Data (Clock Synchronous Mode): Figures 14.20 and 14.21 shows a sample
flowchart for receiving serial data. When switching from the asynchronous mode to the clock
synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to
1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
The procedure for receiving serial data is listed below:
1. SCI initialization: Set the RxD pin using the PFC.
2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the frame MSB (bit 7)
of the current frame is received. If the DMAC or the DTC is started by a receive-data-full
interrupt (RxI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
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